The present invention relates to disk drive circuits and, more particularly, to an apparatus, system and method for biasing a hard disk drive circuit.
Hard disk drives such as the exemplary drive 10 illustrated in FIG. 1 include a stack of magnetically coated platters 12 that are used for storing information. The magnetically coated platters 12 are mounted together in a stacked position through a spindle 14 which may be referred to as a platter stack. The platter stack is typically rotated by a motor that is referred to as a spindle motor or a servo motor (not shown). A space is provided between each platter to allow an arm 18 having a read/write head or slider 20 associated therewith to be positioned on each side of each platter 12 so that information may be stored and retrieved. Information is stored on each side of each platter 12 and is generally organized into sectors, tracks, zones, and cylinders.
Each of the read/write heads or sliders 20 are mounted to one end of the dedicated suspension arm 18 so that each of the read/write heads may be positioned as desired. The opposite end of each of the suspension arms 18 are coupled together at a voice coil motor 16 (VCM) to form one unit or assembly that is positionable by the voice coil motor. Each of the suspension arms 18 are provided in a fixed position relative to each other. The voice coil motor 16 positions all the suspension arms 18 so that the active read/write head 20 is properly positioned for reading or writing information. The read/write heads or sliders 20 may move from at least an inner diameter to an outer diameter of each platter 12 where data is stored. This distance may be referred to as a data stroke.
Hard disk drives also include a variety of electronic circuitry for processing data and for controlling its overall operation. This electronic circuitry may include a pre-amplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry (not shown) to control the operation of the hard disk drive and to properly interface the hard disk drive to a system bus. The pre-amplifier may contain a read pre-amplifier and a write pre-amplifier that is also referred to as a write driver. The pre-amplifier may be implemented in a single integrated circuit or in separate integrated circuits such as a read pre-amplifier and a write pre-amplifier or write driver. The disk control circuitry generally includes a separate microprocessor for executing instructions stored in memory to control the operation and interface of the hard disk drive.
Hard disk drives perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from a system bus and storing the data in the RAM. The microprocessor schedules a series of events to allow the information to be transferred from the RAM to the platters 12 through the write channel. Before the information is transferred, the read/write heads 20 are positioned on the appropriate track and the appropriate sector of the track is located. The data from the RAM is then communicated to the write channel as a digital write signal. The write channel processes the digital write signal and generates an analog write signal. In doing this, the write channel may encode the data so that the data can be more reliably retrieved later. The digital write signal may then be provided to an appropriate read/write head 20 after first being amplified by the pre-amplifier. Writing data to the recording medium or platter 12 is typically performed by applying a current to a coil of the head 20 so that a magnetic field is induced in an adjacent magnetically permeable core, with the core transmitting a magnetic signal across a spacing of the disk to magnetize a small pattern or digital bit of the media associated with the disk.
In a read operation, the appropriate sector to be read is located and data that has been previously written to the platters 12 is read. The appropriate read/write head 20 senses the changes in the magnetic flux and generates a corresponding analog read signal. The analog read signal is provided back to the electronic circuitry where a preamplifier circuit 32 amplifies the analog read signal. The amplified analog read signal is then provided to a read channel circuit 34 where the read channel conditions the signal and detects xe2x80x9czerosxe2x80x9d and xe2x80x9conesxe2x80x9d from the signal to generate a digital read signal. The read channel may condition the signal by amplifying the signal to an appropriate level using, for example, automatic gain control (AGC) techniques. The read channel may then filter the signal to eliminate unwanted high frequency noise, equalize the channel, perform the data recovery from the signal, and format the digital read signal. The digital read signal is then transferred from the read channel and is stored in the RAM (not shown). The microprocessor may then communicate to the host that data is ready to be transferred.
As seen in FIG. 1, many disk drive systems 10 utilize multiple heads 20 due to the multiple platters and use of both sides of the platter. When reading from a particular platter, the head associated therewith is biased at an optimal voltage via a bias current (wherein the unique head itself is the resistive load (RMR)). Therefore in order to bias each head in an optimal manner for read operations, the preamplifier circuit must supply the appropriate bias current to the respective head. Since each head does not exhibit the same resistance (e.g., 30xcexa9, 45xcexa9, etc.), the bias current provided by the preamplifier circuit must change depending on which head has been selected.
Therefore when a portion of data is segmented onto different platters and the data portion is being read, a head switch according to the prior art requires two write steps to a serial port register associated with the preamplifier circuit, wherein one step involves sending a serial, multi-bit code thereto indicating what head is the next or selected head, and another step involves writing a serial, multi-bit code to the serial port register indicating the appropriate bias current to employ for the desired head. Thus a head switch in the prior art required that two write steps to the serial port register be performed in a serial manner. Such sequencing negatively impacts the rate at which data can be read from the disk.
The reason that a prior art head switch requires two successive write steps to the serial port register may be further appreciated with respect to FIG. 2 which illustrates an exemplary bias voltage circuit stage portion 50 of a preamplifier circuit. Bias voltage circuit 50 includes a bipolar transistor Q1 which drives the head which is represented by a resistive load RMR (the value of which will vary from head to head from about 25xcexa9 to about 65xcexa9). A gm amplifier operates to compare the voltages at nodes A and B produce an output signal associated therewith which drives an output node BIAS to charge or discharge capacitor C1. The charge on capacitor C1 sets a bias voltage at the node BIAS which biases the transistor Q1, thereby setting the bias current through the head (RMR). The bias current through RMR influences the voltage at node B which is compared to a reference node A. Thus the influence of node B provides feedback via the gm amplifier and bias capacitor C1 to adjust the bias current appropriately based on the reference voltage at node A. In addition, in order to improve a signal-to-noise ratio (S/N) the bias voltage circuit 50 includes a noise reduction capacitor C2 which, although improving the S/N, slows the bias response of the circuit 50 by retarding the voltage response at node A, the negative impact of which will be discussed below.
When a head switch is to occur, a head select signal opens a switch S1 which decouples the previously selected head and a second switch S2 is closed by a dummy head select signal, thereby activating a dummy transistor Q2 to drive the dummy head (RDUMMY). RDUMMY is typically a resistance having a value of about 10-20% of the lowest expected head resistance. The low value dummy resistance ensures that the node voltage BIAS across C1 gets discharged to a value that will be lower than what is needed for the next head (the selected head). Consequently, when a new head is selected, the transistor (such as Q1) associated with the next selected head will not drive its associated head (RMR) too hard, which would otherwise cause a glitch to damage the respective head. Therefore prior to switching to a new head, a dummy head switch occurs and a sufficient amount of time must pass to ensure that C1 adequately discharges to a safe level.
Subsequently, a current source I1 related to the desired bias current is coupled to node A which drives node A associated with the noise suppression capacitor C2 to a proper reference voltage associated with the desired bias current. However, because C2 does not charge instantaneously, node A xe2x80x9crecoversxe2x80x9d slowly. Because such a slow recovery of node A would result in the node BIAS across C1 charging (thus potentially causing damage to the next selected head), the recovery of node A via capacitor C2 cannot occur concurrently with the C1 recovery discussed above. Consequently, C2 recovery in prior art systems occurs after C1 recovery, thereby disadvantageously causing increased delay.
Therefore the prior art methodology for switching from one head to another may be illustrated in FIG. 3 and designated at reference numeral 80. The prior art method of switching heads required two separate, serially performed steps: (1) a head switch 82, and (2) a current bias switch 84. In particular, the head switch 82 included a step of writing a multi-bit code to a serial port register to indicate the next desired head (step 86), a switch to the dummy head (step 88) to initiate a discharge of C1, and a wait period (step 90) to allow C1 to sufficiently discharge to a safe level to avoid a glitch at the next head when connecting thereto. Once the wait period was complete and the next head had been selected, a second write to the serial port register was made to indicate the desired bias current for the next selected head (step 92). Subsequently, another wait period was initiated to allow C2 to recover to a predetermined level at step 94.
There is a need in the art for speed improvement in switching from one head to another in a hard disk drive mass storage device.
The present invention relates to a system and method of switching heads in a hard disk drive mass storage system which overcomes the disadvantages associated with the prior art. In particular, the present invention relates to a system and method of switching heads in which the head switch and current bias switch associated therewith are performed concurrently with one another, thereby allowing such steps to be achieved in a single write step to the serial port register, and improving a rate at which the head switch is accomplished.
In accordance with one aspect of the present invention, a preamplifier circuit is disclosed having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit and a head select boost recovery circuit both of which are operatively coupled to the bias voltage circuit stage. The current bias boost recovery circuit is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. In addition, the head select boost recovery circuit is configured to selectively increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the current bias boost recovery circuit and the head select boost recovery circuit are operable to facilitate a concurrent head switch and current bias switch.
According to another aspect of the present invention, the current bias boost recovery circuit comprises a voltage level detection circuit and a target voltage application circuit operatively coupled together. The voltage level detection circuit is configured to determine a target voltage associated with the noise reduction capacitor, for example, a reference node voltage having a value associated with the desired bias current for a given head. The target voltage application circuit is configured to selectively apply the target voltage determined by the voltage level detection circuit to the node of the noise reduction capacitor, thereby increasing substantially a rate at which the noise reduction capacitor charges to the target voltage. Consequently, the recovery associated with the noise reduction capacitor occurs extremely quickly, and brings the reference node associated therewith to its desired reference value in a timely manner.
According to still another aspect of the present invention, the voltage level detection circuit comprises a current mirror circuit and a voltage generation circuit operatively coupled to the current mirror circuit. The current mirror circuit is configured to generate a current having a magnitude which is related to the desired target voltage and the voltage generation circuit is configured to generate a voltage level approximating the target voltage using the generated current. Once generated, the target value application circuit is operable to selectively couple the generated target voltage to the reference node for a quick recovery across the noise reduction capacitor, thereby improving recovery associated therewith.
According to yet another aspect of the present invention, the head select boost recovery circuit comprises a differential voltage detection circuit and a selectively activatable drive circuit associated therewith. The differential voltage detection circuit is configured to monitor a difference between a reference node and another node associated with the head bias current, and is further configured to activate the drive circuit if a difference between the nodes exceeds a predetermined threshold. The drive circuit is configured to drive, when activated, a bias capacitor associated therewith to increase a rate of charging or discharging associated therewith, thereby minimizing the difference between the nodes in a timely manner. In accordance with an exemplary aspect of the present invention, the differential voltage detection circuit and the selectively activatable drive circuit comprise a differential amplifier having an offset trigger voltage associated therewith, wherein the offset trigger voltage is related to the predetermined threshold.
To the accomplishment of the foregoing and related ends, the invention, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.